This invention relates to a test pattern converter and conversion method thereof for converting the format of test patterns used to test semiconductor devices such as LSIs, and more particularly, to a test pattern converter and conversion method thereof for converting cycle-based test patterns into event-based test patterns with use of a tester simulator.
In testing semiconductor devices such as LSIs, a semiconductor test system provides input test signals to a semiconductor device under test. The output signal from the semiconductor device under test resulting from the input test signal is sampled at timings of strobes, and compared with predetermined expected values to check if the two signals match with one another, thereby determining whether the semiconductor device under test functions correctly. Generally, the input test signal and strobe are collectively called a xe2x80x9ctest patternxe2x80x9d.
Many different test patterns are produced depending on particular test types or test purposes for semiconductor devices to be tested, and are stored in a storage medium such as a hard disc as test pattern files. Prior to beginning a test for semiconductor devices, the applicable test patterns are installed in the semiconductor test system, where the test patterns are generated upon starting the test operation and the test patterns are applied to the semiconductor device under test.
The majority of the existing semiconductor test systems today are structured to generate test patterns using test pattern data described in a cycle format (hereafter xe2x80x9ccycle-based test systemxe2x80x9d). The cycle format is a method of formulating pattern data in which the test patterns such as input test signals to be generated by the semiconductor test system are divided into each predetermined time (test cycle), and defining the kinds of waveforms, logic, and timings with respect to those test cycles. The details of the cycle format will be explained later.
Recently, an event-based semiconductor test system (hereafter xe2x80x9cevent-based test systemxe2x80x9d) structured by an architecture different from the cycle-based test system has been proposed. The event-based test system generates test patterns by using the test pattern data described in an event format. The event format expresses the test pattern waveforms to be generated by the semiconductor test system by each and every change point (i.e., rising edges, falling edges) of the waveforms and its timing data. Therefore, processes such as dividing the test patterns at every test cycle are not involved in this format. The details of the event format will be explained later.
In the case of using the cycle format, test program descriptions become complicated and the execution of the test program will require a complicated test system operation, although the amount of data in the test program becomes small. On the contrary, in the case of using the event format, the test program description and its execution are more simplified, and the flexibility of the test system becomes greater. However, the amount of data in the event-based test patterns can increase, therefore requiring a larger memory capacity in the test system which increases the test system cost. In recent years, however, memory capacity per unit price has been dramatically increasing, thus, the cost increase of memories is no longer thought to be a major problem.
FIG. 1 is a block diagram showing an example of a basic structure of the cycle-based test system. In this diagram, a tester processor 11 is an exclusive processor installed in the test system, and controls the operation of the test system through a tester bus. Based on pattern data from the tester processor 11, a pattern generator 12 provides timing data and waveform data to a timing generator 13 and a wave formatter 14, respectively. Based on the waveform data from the pattern generator 12 and the timing data from the timing generator 13, the wave formatter 14 formats the test patterns. The test patterns produced by the wave formatter 14 are then supplied to a device under test (DUT) 19 through a driver 15 provided in a pin electronics circuit 20.
DUT 19 responds to the test patterns and generates output signals. The output signals are transmitted to an analog comparator 16 in the pin electronics circuit 20. At timings of the strobes, the analog comparator 16 converts the output signals from DUT 19 into logic signals with respect to predetermined threshold levels, and sends the result to a logic comparator 17. In the logic comparator 17, the logic data from DUT 19 and expected logic data formed by the pattern generator 12 are compared with each other. The results of comparison are stored in a failure memory 18 in the addresses corresponding to the addresses of a memory which stores the test patterns or to the addresses of DUT 19.
FIG. 2 is a block diagram showing an example of a basic structure of the event-based test system. The event-based test system in this example is comprised of a host computer 42, a bus interface 43, an internal bus 45, an address control logic 48, a failure memory 47, an event memory configured by an event count memory 50 and an event vernier memory 51, an event summing and scaling logic 52, an event generator 24, and a pin electronics circuit 26. A device under test (DUT) 28 is connected to the pin electronics circuit 26.
As an example, the host computer 42 is a work station with a UNIX operating system. The host computer 42 functions as a user interface for the user to instruct the start and stop of the test, to load test programs and other test conditions, or to conduct the test result analysis at the host computer. The host computer 42 interfaces with the hardware test system through the system bus 44 and the bus interface 43.
The internal bus 45 is a bus within the hardware test system. As an example, the address control logic 48 is a tester processor exclusive to the hardware test system, and therefore the user cannot have access to it. Based on the test programs and test conditions from the host computer 42, the address control logic 48 supplies the instructions to other functional blocks within the test system. The failure memory 47 stores the test result such as failure information concerning the DUT 28 in the addresses defined by the address control logic 48. The information stored in the failure memory 47 is used in a failure analysis stage of the device under test.
The address control logic 48 provides the address data to the failure memory 47 and the event memory comprised of the event count memory 50 and the event vernier memory 51. The event memory stores the event timing data which expresses the timing of each event (i.e., change point of 1 to 0 or 0 to 1). For example, the timing data for each event is divided into integral data representing an integer multiple of a reference clock period and fractional data representing a fraction of the reference clock period. For example, the integral data is stored in the event count memory 50 and the fractional data is stored in the event vernier memory 51.
The event summing and scaling logic 52 accumulates the event timing data and modifies a multiplication ratio of the timing data, and expresses the timing of each event as a total timing (delay time) from a predetermined reference time. Based on the total timing data, the event generator 24 generates a test pattern (drive event), and provides the test pattern to DUT 28 through the pin electronics circuit 26. By comparing the response output signals of DUT 28 with the expected pattern (sampling event), the test system determines pass/fail regarding a particular pin of DUT 28.
As explained above, in the event-based test system, the data configuration in a test program used therein is simple, and therefore, allows the test program to be easily created as well as enables the test system to configure in such a way that each test pin in the test system functions independently from one another. As a result, the test system is able to perform with high flexibility. Based on such advantages, the event-based test system will be widely used in the near future.
The semiconductor test systems currently in practical use today operate with test programs using the cycle-based test patterns. Therefore, test system users have resources of many test pattern files described in the cycle-based format. If such assets of test patterns can be converted into an event-based format, then with the implementation of the event-based tester, the time and cost to create new test programs can be saved. What is needed is a pattern converter which can easily convert the existing cycle-based test patterns into event-based test patterns.
Therefore, it is an object of the present invention to provide a test pattern converter and a test pattern conversion method for converting the test pattern data created for the cycle-based test system into event-based test pattern data to be used in the event-based test system.
It is another object of the present invention to provide a test pattern converter for converting the cycle-based test pattern data into an event-based test pattern data with use of a tester simulator.
It is a further object of the present invention to provide a test pattern converter for effectively utilizing the existing test pattern resources by converting the test pattern data in the cycle format into test pattern data in the event format.
The test pattern converter of the present invention includes a pattern controller for sequentially reading out pattern count data indicating a pattern number assigned to specify a test cycle in a test pattern described in the cycle format and timing set data specifying a type of time length of the test cycle indicated by the pattern number; a cycle generator for reading out, based on the timing set data from the pattern controller, a value of the time length of the test cycle corresponding to the pattern number; a pattern data generator for reading out, based on the pattern count data from the pattern controller, a logic value (pattern data) of a test pattern waveform corresponding to the pattern number; a waveform data generator for reading out, based on the timing set data from the pattern controller, format data indicating a type of the test pattern waveform in the test cycle corresponding to the timing set data and timing data indicating a delay time of a rising edge or a falling edge of the test pattern waveform from a start point of the test cycle; and a calculation unit for forming the test pattern in the event format based on the data from the pattern data generator and from the waveform data generator wherein the event format test pattern describes the events by combinations of change points of the test waveform and time differences of the change points from a reference point.
The calculation unit accumulates all of time lengths of the timing set data corresponding to all of pattern numbers previous to the current pattern number and adds a delay time of a rising edge or a falling edge of the test pattern waveform of the current pattern number to the accumulated value, thereby determining an overall delay time of the rising or falling edge (current event) relative to the reference point.
The test pattern data formed by the calculation unit is stored in a storage medium, thereby producing a test pattern file of an event format. The description of the test pattern in the event format does not include information for dividing the test pattern on a time axis.
Another aspect of the present invention is a method of converting test pattern data described in a cycle format for testing a semiconductor device to test pattern data in an event format. The method includes the following steps of: sequentially reading out pattern count data indicating a pattern number assigned to specify a test cycle in a test pattern described in the cycle format and timing set data specifying a type of time length of the test cycle indicated by the pattern number; reading out a value of the time length of the test cycle corresponding to the pattern number based on the timing set data from the pattern controller; reading out a logic value (pattern data) of a test pattern waveform corresponding to the pattern number based on the pattern count data from the pattern controller; reading out format data indicating a type of the test pattern waveform in the test cycle corresponding to the timing set data and timing data indicating a delay time of a rising edge or a falling edge of the test pattern waveform from a start point of the test cycle based on the timing set data from the pattern controller; and forming the test pattern in the event format based on the data from the pattern data generator and from the waveform data generator wherein the event format test pattern describes the events by combinations of change points of the test waveform and time differences of the change points from a reference point.
With use of the test pattern converter of the present invention, the test pattern data already in a cycle-based format can be easily converted into an event-based format. Therefore, the test pattern assets created for the cycle-based test systems can be effectively utilized for event-based test systems, and the time and cost for newly creating event-based test patterns are saved, achieving the reduction in the overall test cost.